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c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - a u g . , 2 0 1 2 a p w 7 1 5 3 / a / b w w w . a n p e c . c o m . t w 1 a n p e c r e s e r v e s t h e r i g h t t o m a k e c h a n g e s t o i m p r o v e r e l i a b i l i t y o r m a n u f a c t u r a b i l i t y w i t h o u t n o t i c e , a n d a d v i s e c u s t o m e r s t o o b t a i n t h e l a t e s t v e r s i o n o f r e l e v a n t i n f o r m a t i o n t o v e r i f y b e f o r e p l a c i n g o r d e r s . 3 a 5 v 2 m h z s y n c h r o n o u s b u c k c o n v e r t e r f e a t u r e s high efficiency up to 95% - pfm/pwm mode operation adjustable output voltage from 0.8v to vin integrated 110m w high/low side mosfet programmable switching frequency: 300khz to 2mhz low dropout operation: 100% duty cycle stable with low esr capacitors power-on-reset detection on vdd and pvdd integrate soft-start and soft-off over-temperature protection over-voltage protection under-voltage protection high/low side current-limit power good indicator (apw7153a/b) enable/shutdown function small tdfn3x3-10 and sop-8p packages lead free and green devices available (rohs compliant) a p p l i c a t i o n s g e n e r a l d e s c r i p t i o n lcd minitor/tv set-top box dsl, switch hub notebook computer portable instrument s i m p l i f i e d a p p l i c a t i o n c i r c u i t p i n c o n f i g u r a t i o n s apw7153/a/b is a 3a synchronous buck converter with integrated 110m w power mosfets. the apw7153/a/b is designed with a current-mode control scheme; it can convert wide input voltage of 2.6v to 5.5v to the output voltage adjustable from 0.8v to 5.5v to provide excellent output voltage regulation. the apw7153/a/b is equipped with an pfm/pwm mode operation. at light load, the ic operates in the pfm mode to reduce the switching losses. at heavy load, the ic works in pwm. at pwm mode, the switching frequency is set by the external resistor. the apw7153/a/b is also equipped with power-on-reset, soft-start, soft-stop, and whole protections (under-voltage, over-voltage, over-temperature and current-limit) into a single package. this device, available tdfn3x3-10 and sop-8p provides a very compact system solution external components and pcb area. the pin 2 and 5 must be connected to the pin 11 (exposed pad) 11 the pin 2 and 4 must be connected to the pin 9 (exposed pad) 9 apw7153/a/b v dd p vdd v in v out lx 3 8 comp shdn/rt 1 gnd 2 7 fb 5 pvdd 6 vdd sop-8p (top view) pgnd 4 apw7153 9 expose pad lx 3 10 comp shdn/rt 1 gnd 2 pgnd 5 9 fb 7 pvdd 8 vdd tdfn3x3-10 (top view) 11 expose pad lx 4 6 pvdd apw7153 lx 3 10 comp en/rt 1 gnd 2 pgnd 5 9 fb 7 vdd 8 pok tdfn3x3-10 (top view) 11 expose pad lx 4 6 pvdd apw7153a lx 3 10 comp shdn/rt 1 gnd 2 pgnd 5 9 fb 7 vdd 8 pok tdfn3x3-10 (top view) 11 expose pad lx 4 6 pvdd apw7153b
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - a u g . , 2 0 1 2 a p w 7 1 5 3 / a / b w w w . a n p e c . c o m . t w 2 symbol parameter rating unit v vdd , v pvdd input supply voltage - 0.3 ~ 6 v >20ns pulse width - 1 ~v pvdd +0.3 v v lx lx to gnd voltage <20ns pulse width - 3 ~v pvdd +3 v shdn/rt , fb, comp , pok to gnd voltage - 0.3 ~ 6 v pgnd pgnd to gnd voltage - 0.3 ~ +0.3 v p d power dissipation internally limited w t j junction temperature 150 o c t stg storage temperature - 65 ~ 150 o c t sdr maximum lead soldering temperature , 10 seconds 26 0 o c o r d e r i n g a n d m a r k i n g i n f o r m a t i o n a b s o l u t e m a x i m u m r a t i n g s ( n o t e 1 ) t h e r m a l c h a r a c t e r i s t i c s symbol parameter typical value unit q ja junction - to - ambient resistance in f ree a ir (note 2) tdfn3x3 - 10 sop - 8p 50 80 o c/w q jc junction - to - case resistance in f ree a ir (note 3) tdfn3x3 - 10 sop - 8p 10 20 o c/w n o t e : a n p e c l e a d - f r e e p r o d u c t s c o n t a i n m o l d i n g c o m p o u n d s / d i e a t t a c h m a t e r i a l s a n d 1 0 0 % m a t t e t i n p l a t e t e r m i n a t i o n f i n i s h ; w h i c h a r e f u l l y c o m p l i a n t w i t h r o h s . a n p e c l e a d - f r e e p r o d u c t s m e e t o r e x c e e d t h e l e a d - f r e e r e q u i r e m e n t s o f i p c / j e d e c j - s t d - 0 2 0 d f o r m s l c l a s s i f i c a t i o n a t l e a d - f r e e p e a k r e f l o w t e m p e r a t u r e . a n p e c d e f i n e s ? g r e e n ? t o m e a n l e a d - f r e e ( r o h s c o m p l i a n t ) a n d h a l o g e n f r e e ( b r o r c l d o e s n o t e x c e e d 9 0 0 p p m b y w e i g h t i n h o m o g e n e o u s m a t e r i a l a n d t o t a l o f b r a n d c l d o e s n o t e x c e e d 1 5 0 0 p p m b y w e i g h t ) . note1: stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom- mended operating conditions" is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2: q ja is measured with the component mounted on a high effective thermal conductivity test board in free air. the exposed pad of tdfn3x3-10 and sop-8p is soldered directly on the pcb. note 3: the case temperature is measured at the center of the exposed pad on the underside of the tdfn3x3-10 and sop-8p packages. package code qb : tdfn3x3-10 ka : sop-8p operating ambient temperature range i : -40 to 85 o c handling code tr : tape & reel assembly material g : halogen and lead free device apw7153/a/b qb: apw 7153 xxxxx xxxxx - date code apw7153/a/b handling code temperature range package code assembly material apw 7153a xxxxx apw7153 ka: apw7153 xxxxx xxxxx - date code apw 7153b xxxxx
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - a u g . , 2 0 1 2 a p w 7 1 5 3 / a / b w w w . a n p e c . c o m . t w 3 r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s ( n o t e 4 ) symbol parameter range unit v vdd control and driver supply voltage 2.6 ~ 5.5 v v pvdd input supply voltage 1. 5~5.5 v v out converter output voltage 0.8~5.5 v i out converter output current 0~3 a t a ambient temperature - 40 ~ 85 o c t j junction temperature - 4 0 ~ 125 o c e l e c t r i c a l c h a r a c t e r i s t i c s apw7153/a/b symbol parameter test conditions min. typ. max. unit supply current i vdd vdd supply current v fb =1v - 460 - m a i vdd_sdh vdd shutdown supply current shdn/rt=vdd - - 1 m a i vdd_sdl vdd shutdown supply current shdn/rt=gnd - - 10 m a power - o n - r eset (por) vdd por voltage threshold v in rising 2.3 2.4 2.5 v vdd debounce time - 100 - m s vdd por hysteresis 0.1 0.2 0.3 v pvdd por voltage threshold 1.5 1.6 1.7 v pvdd por debounce - 10 - m s pvdd por hysteresis - 50 - mv reference v oltage apw7153/b - 0.8 - v ref reference voltage regulated on fb pin apw7153a - 0.5 - v t j =25c, i out =10ma , v dd = 5 v - 0.5 - +0.5 % output voltage accuracy i out =10ma ~3a, v dd = 2.6~5 v - 0.8 - +0.8 % oscillator and duty cycle f osc oscillator frequency 0.3 - 2 mhz oscillator frequency r t =332k w 0.8 1 1.2 mhz maximum converter ? s duty - 100 - % minimum on time - 90 - ns power mosfet high side p - mosfet resistance i lx =0.5a, t a =25 c - 110 160 m w low side n - mosfet resistance i lx =0.5a, t a =25 c - 110 160 m w high / low side mosfet leakage cur rent - - 10 m a note 4: refer to the typical application circuit. unless otherwise specified, these specifications apply over v vdd =v pvdd =3.3v, t a = -40 ~ 85 o c. typical values are at t a =25 o c.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - a u g . , 2 0 1 2 a p w 7 1 5 3 / a / b w w w . a n p e c . c o m . t w 4 e l e c t r i c a l c h a r a c t e r i s t i c s ( c o n t . ) apw7153/a/b symbol parameter test conditions min. typ. max. unit current - mode pwm converter gm error amplifier transconductance - 550 - m a/v error amplifier dc gain comp=nc - 80 - db current sense transresistance - 500 - m w t d dead time (no te 5) - 20 - ns protecti ons i lim high side mosfet current - limit peak current 4.0 4.5 5.0 a t otp over - temperature trip point (note 5) - 160 - c over - temperature hysteresis - 50 - c over - voltage protection threshold 119 125 131 %v out under - vo ltage protection threshold 44 50 56 % low side mosfet current - limit from drain to source 0.7 - 1.6 a soft - start, enable and input currents soft - start time 1 1.5 2 ms v shdn shdn shutdown threshold v shdn > shdn s hutdown threshold, ic shutdown - v vd d - 0.9 v vdd - 0.4 v pok in from lower (pok goes high) 85 87.5 90 %v out pok low hysteresis (pok goes high) - 5 - %v out pok in from higher (pok goes high) 110 112.5 115 %v out pok threshold pok high hysteresis (pok goes low) - 5 - %v out power go od pull low resistance - 100 - w power good debounce - 0.5 - ms unless otherwise specified, these specifications apply over v vdd =v pvdd =3.3v, t a = -40 ~ 85 o c. typical values are at t a =25 o c. n o t e 5 : g u a r a n t e e b y d e s i g n .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - a u g . , 2 0 1 2 a p w 7 1 5 3 / a / b w w w . a n p e c . c o m . t w 5 r e f e r t o t h e a p p l i c a t i o n c i r c u i t i n t h e s e c t i o n ? t y p i c a l a p p l i c a t i o n c i r c u i t s ? , v i n = 5 v , t a = 2 5 o c , u n l e s s o t h e r w i s e s p e c i f i e d . t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s oscillator frequency vs. rt resistance efficiency vs. output current reference voltage vs. supply voltage supply voltage, v vdd (v) r e f e r e n c e v o l t a g e , v r e f ( m v ) 780 785 790 795 800 805 810 815 820 2 2.5 3 3.5 4 4.5 5 5.5 no switch quiescent current vs. supply voltage peak current-limit vs. supply voltage 0 1 2 3 4 5 6 2.5 3 3.5 4 4.5 5 5.5 supply voltage, v vdd (v) p e a k c u r r e n t l i m i t , i l i m ( a ) efficiency vs. output current 200 250 300 350 400 450 2 2.5 3 3.5 4 4.5 5 5.5 supply voltage, v vdd (v) n o s w i t c h q u i e s c e n t c u r r e n t , i v d d ( m a ) 0.01 0.1 1 10 output current, i out (a) e f f i c i e n c y ( % ) 50 55 60 65 70 75 80 85 90 95 100 v in =5v v out =3.3v r t =330k 50 55 60 65 70 75 80 85 90 95 100 0.01 0.1 1 10 output current, i out (a) e f f i c i e n c y ( % ) v in =5v v out =1.8v r t =330k o s c i l l a t o r f r e q u e n c y , f o s c ( m h z ) rt resistance, r rt (k w ) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 200 400 600 800 1000 1200 1400 rt=330k for 1mhz rt=1.3m for 300khz
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - a u g . , 2 0 1 2 a p w 7 1 5 3 / a / b w w w . a n p e c . c o m . t w 6 o p e r a t i n g w a v e f o r m s start-up with no load en, 2v/div i in , 200ma/div pok, 5v/div v out , 1v/div, dc 0.5ms/div start-up with 3a load load transient response 10ma 3a slew rate = 3a/20 m s 100 m s/div v out , 100mv/div, ac i out , 1a/div v out =1.8v normal operating 500ns/div v out , 50mv/div, ac v lx , 2v/div i out , 1a/div 0.5ms/div en, 2v/div i in , 1a/div pok, 5v/div v out , 1v/div, dc
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - a u g . , 2 0 1 2 a p w 7 1 5 3 / a / b w w w . a n p e c . c o m . t w 7 p i n d e s c r i p t i o n pin tdfn3x3 - 10 sop - 8p apw7153 apw7153a apw7153b apw7153 name function 1 - 1 1 shdn/rt shutdown/enable and oscillator input. connecting a resistor to gnd sets the switching frequency. pull the pin to vdd to shut down the device. do leave the pin float ing. - 1 - - en/rt shutdown/enable and oscillator input. connecting a resistor to vdd sets the switching frequency. pull the pin to gnd to shut down the device. do leave the pin floating. 2 2 2 2 gnd signal ground. ground of mosfet gate drivers and con trol circuitry. 3, 4 3, 4 3, 4 3 lx power switching output. lx is the junction of the high - side and low - side power mosfets to supply power to the output lc filter. 5 5 5 4 pgnd power ground. the source of the n - channel power mosfet. connect this pin to t he system ground with lowest impedance. 6, 7 6 6 5 pvdd power input. pvdd supplies the step - down converter switches. connecting a ceramic bypass capacitor from pvdd to pgnd to eliminate switching noise and voltage ripple on the input to the ic. 8 7 7 6 v dd control circuitry supply input. vdd supplies the control circuitry, gate drivers. connecting a ceramic bypass capacitor from vdd to gnd to eliminate switching noise and voltage ripple on the input to the ic. - 8 8 - pok power good output. this pin is o pen - drain logic output that is pulled to ground when the output voltage is not within ? 12.5% of regulation point. 9 9 9 7 fb output feedback input. the apw7153/a senses the feedback voltage via fb and regulates the voltage at 0.8v. connecting fb with a re sistor - divider from the converter ? s output sets the output voltage. 10 10 10 8 comp output of the error amplifier. connect a series rc network from comp to gnd to compensate the regulation control loop. in some cases, an additional capacitor from comp to gnd is required. 11 11 11 9 exposed pad connect the exposed pad to the system ground plan with large copper area for dissipating heat into the ambient air.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - a u g . , 2 0 1 2 a p w 7 1 5 3 / a / b w w w . a n p e c . c o m . t w 8 b l o c k d i a g r a m apw7153 apw7153a lx gate control fault logics error amplifier fb inhibit pgnd por power-on- reset current sense amplifier comp oscillator slope compensation current compartor over- temperature protection current -limit gat e gm 1v otp current sense amplifier loc loc vdd shdn/rt 0.4 shutdown gnd gate driver uvp v ref ovp zero crossing amplifier 0.8v pvdd soft-start lx gate control fault logics error amplifier fb inhibit pgnd por power-on- reset current sense amplifier comp oscillator slope compensation current compartor over- temperature protection current -limit gat e gm pvdd 3 5 6 9 10 0.625v otp current sense amplifier loc loc vdd 7 4 lx en/rt 1 0.25v 8 shutdown pok gnd gate driver uvp v ref ovp 2 0.5625v 0.4375v 0.5v zero crossing comparator soft-start
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - a u g . , 2 0 1 2 a p w 7 1 5 3 / a / b w w w . a n p e c . c o m . t w 9 b l o c k d i a g r a m apw7153b lx gate control fault logics error amplifier fb inhibit pgnd por power-on- reset current sense amplifier comp oscillator slope compensation current compartor over- temperature protection current -limit gat e gm pvdd 3 5 6 9 10 1v otp current sense amplifier loc loc vdd 7 4 lx shdn/rt 1 0.4v soft-start 8 shutdown pok gnd gate driver uvp v ref ovp 2 0.9v 0.7v 0.8v zero crossing comparator
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - a u g . , 2 0 1 2 a p w 7 1 5 3 / a / b w w w . a n p e c . c o m . t w 1 0 t y p i c a l a p p l i c a t i o n c i r c u i t apw7153 pvdd vdd pgnd lx fb v out 1.8v/3a c out 22 m fx2 r1 25k r2 20k cc 100pf rc 30k comp c in 22 m f r t 332k c2 1 m f cff 22pf gnd r4 2r2 shdn/rt l1 2.2 m h r3 1m v in 5v on off apw7153a pvdd 6 vdd pgnd 5 lx 3,4 fb 9 7 v out 1.8v/3a c out 22 m fx2 r1 39k r2 15k cc 100pf rc 30k comp 10 c in 22 m f pok c2 1 m f cff 22pf gnd 2 r4 2r2 8 1 en/rt l1 2.2 m h r3 1.8m r5 100k v in 5v off on apw7153b pvdd 6 vdd pgnd 5 lx 3,4 fb 9 7 v out 1.8v/3a c out 22 m fx2 r1 25k r2 20k cc 100pf rc 30k comp 10 c in 22 m f pok r t 332k c2 1 m f cff 22pf gnd 2 r4 2r2 8 1 shdn/rt l1 2.2 m h r3 1m r5 100k v in 5v on off
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - a u g . , 2 0 1 2 a p w 7 1 5 3 / a / b w w w . a n p e c . c o m . t w 1 1 f u n c t i o n d e s c r i p t i o n v d d a n d p v d d p o w e r - o n - r e s e t ( p o r ) the apw7153/a/b keeps monitoring the voltage on vdd and pvdd pins to prevent wrong logic operations which may occur when vdd or pvdd voltage is not high enough for internal control circuitry to operate. the vdd por ris- ing threshold is 2.4v (typical) with 0.2v hysteresis and pvdd por rising threshold is 1.7v with 0.05v hysteresis. during start-up, the vdd and pvdd voltage must exceed the enable voltage threshold. then, the ic starts a start- up process and ramps up the output voltage to the volt- age target. output under-voltage protection (uvp) in the operational process, if a short-circuit occurs, the output voltage will drop quickly. before the current-limit circuit responds, the output voltage will fall out of the re- quired regulation range. the under-voltage continually monitors the fb voltage after soft-start is completed. if a load step is strong enough to pull the output voltage lower than the under-voltage threshold, the ic shuts down con- verter?s output. the under-voltage threshold is 50% of the nominal out- put voltage. the under-voltage comparator has a built-in 3 m s noise filter to prevent the chips from wrong uvp shut- down being caused by noise. apw7153/a/b will be latched after under-voltage protection. over-voltage protection (ovp) the over-voltage function monitors the output voltage by fb pin. when the fb voltage increases over 125% of the reference voltage due to the high-side mosfet failure or for other reasons, the over-voltage protection compara- tor will force the low-side mosfet gate driver to be high. this action actively pulls down the output voltage and eventually attempts to blow the internal bonding wires. as soon as the output voltage is within regulation, the ovp comparator is disengaged. the chip will restore its normal operation. o v e r - t e m p e r a t u r e p r o t e c t i o n ( o t p ) the over-temperature circuit limits the junction tempera- ture of the apw7153/a/b. when the junction temperature exceeds t j =+160 o c, a thermal sensor turns off the both current-limit protection the apw7153/a/b monitors the output current, flows through the high-side and low-side power mosfets, and limits the current peak at current-limit level to prevent the ic from damaging during overload, short-circuit, and over- voltage conditions. typical high side power mosfet cur- rent-limit is 4.5a, and low side mosfet current-limit is 1.6a maximum. power mosfets, allowing the devices to cool. the ther- mal sensor allows the converters to start a start-up pro- cess and to regulate the output voltage again after the junction temperature cools by 50 o c. the otp is designed with a 50 o c hysteresis to lower the average t j during continuous thermal overload conditions, increasing life- time of the apw7153/a/b. soft-start t h e a p w 7 1 5 3 / a / b h a s a b u i l t - i n s o f t - s t a r t t o c o n t r o l t h e r i s e r a t e o f t h e o u t p u t v o l t a g e a n d l i m i t t h e i n p u t c u r r e n t s u r g e d u r i n g s t a r t - u p . d u r i n g s o f t - s t a r t , a n i n t e r n a l v o l t - a g e r a m p c o n n e c t e d t o o n e o f t h e p o s i t i v e i n p u t s o f t h e e r r o r a m p l i f i e r , r i s e s u p f r o m 0 v t o 0 . 9 5 v t o r e p l a c e t h e r e f e r e n c e v o l t a g e , v r e f u n t i l t h e v o l t a g e r a m p r e a c h e s t h e r e f e r e n c e v o l t a g e . d u r i n g s o f t - s t a r t w i t h o u t o u t p u t o v e r - v o l t a g e , t h e a p w 7 1 5 3 / a / b c o n v e r t e r ? s s i n k i n g c a p a b i l i t y i s d i s a b l e d u n t i l t h e o u t p u t v o l t a g e r e a c h e s t h e v o l t a g e t a r g e t . s o f t - o f f a t t h e m o m e n t o f s h u t d o w n c o n t r o l l e d b y s h d n / r t s i g n a l , u n d e r - v o l t a g e e v e n t o r o v e r - t e m p e r a t u r e p r o t e c t i o n , t h e a p w 7 1 5 3 / a / b i n i t i a t e s a s o f t - s t o p p r o c e s s t o d i s c h a r g e t h e o u t p u t v o l t a g e i n t h e o u t p u t c a p a c i t o r s . c e r t a i n l y , t h e l o a d c u r r e n t a l s o d i s c h a r g e s t h e o u t p u t v o l t a g e . d u r i n g s o f t - s t o p , t h e i n t e r n a l v o l t a g e r a m p ( v r a m p ) f a l l s d o w n r i s e s f r o m 0 . 9 5 v t o 0 v t o r e p l a c e t h e r e f e r e n c e v o l t a g e . t h e r e f o r e , t h e o u t p u t v o l t a g e f a l l s d o w n s l o w l y a t t h e l i g h t l o a d . a f t e r t h e s o f t - s t o p i n t e r v a l e l a p s e s , t h e s o f t - s t o p p r o c e s s e n d s a n d t h e i c t u r n s o n t h e l o w - s i d e p o w e r m o s f e t .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - a u g . , 2 0 1 2 a p w 7 1 5 3 / a / b w w w . a n p e c . c o m . t w 1 2 f u n c t i o n d e s c r i p t i o n ( c o n t . ) switching frequency and shutdown/enable the shdn/rt pin is a multi-function pin that is used to control the switching frequency and shutdown/enable function of apw7153/a/b. the switching frequency is set by the external resistor that is connected between shdn/ rt and gnd. the value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator. the shdn/rt pin also provides shutdown/enable function. pulling the pin to vdd or gnd, apw7153/a/b initiates a soft-stop process and shutdown the ic. p o w e r g o o d i n d i c a t o r ( a p w 7 1 5 3 a / b ) pok is actively held low in shutdown and soft-start status. in the soft-start process, the pok is an open-drain. when the soft-start is finished, the pok is released. in normal operation, the pok window is from 87.5% to 112.5% of the converter reference voltage. when the output voltage has to stay within this window, pok signal will become high after 0.5ms internal delay. when the output voltage outruns 85% or 115% of the target voltage, pok signal will be pulled low immediately. in order to prevent false pok drop, capacitors need to parallel at the output to confine the voltage deviation with severe load step transient.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - a u g . , 2 0 1 2 a p w 7 1 5 3 / a / b w w w . a n p e c . c o m . t w 1 3 a p p l i c a t i o n i n f o r m a t i o n input capacitor selection because buck converters have a pulsating input current, a low esr input capacitor is required. this results in the best input voltage filtering, minimizing the interference with other circuits caused by high input voltage spikes. also, the input capacitor must be sufficiently large to sta- bilize the input voltage during heavy load transients. for good input voltage filtering, usually a 22 m f input capaci- tor is sufficient. it can be increased without any limit for better input voltage filtering. ceramic capacitors show better performance because of the low esr value, and they are less sensitive against voltage transients and spikes compared to tantalum capacitors. place the input capacitor as close as possible to the input and gnd pin of the device for better performance. inductor selection for high efficiencies, the inductor should have a low dc resistance to minimize conduction losses. especially at high-switching frequencies the core material has a higher impact on efficiency. when using small chip inductors, the efficiency is reduced mainly due to higher inductor core losses. this needs to be considered when select- ing the appropriate inductor. the inductor value deter- mines the inductor ripple current. the larger the inductor value, the smaller the inductor ripple current and the lower the conduction losses of the converter. conversely, larger inductor values cause a slower load transient response. a reasonable starting point for setting ripple current, d i l, is 40% of maximum output current. the recommended inductor value can be calculated as below: l sw in out out i f v v 1 v l d ? ? ? ? ? - 3 i l(max) = i out(max) + 1/2 x d i l to avoid saturation of the inductor, the inductor should be rated at least for the maximum output current of the con- verter plus the inductor ripple current. output voltage setting in the adjustable version, the output voltage is set by a resistive divider. the external resistive divider is con- nected to the output, allowing remote voltage sensing as shown in ?typical application circuits?. a suggestion of maximum value of r2 is 300k w to keep the minimum current that provides enough noise rejection ability through the resistor divider. the output voltage can be calculated as below: ? ? ? ? ? + = 2 r 1 r 1 v v ref out r2 300k w apw7153 fb gnd v out r1 1m w output capacitor selection the current-mode control scheme of the apw7153 al- lows the use of tiny ceramic capacitors. the higher ca- pacitor value provides the good load transients response. ceramic capacitors with low esr values have the lowest output voltage ripple and are recommended. if required, tantalum capacitors may be used as well. the output ripple is the sum of the voltages across the esr and the ideal output capacitor. ? ? ? ? ? + ? ? ? ? ? - @ d out sw sw in out out out c f 8 1 esr l f v v 1 v v when choosing the input and output ceramic capacitors, choose the x5r or x7r dielectric formulations. these dielectrics have the best temperature and voltage char- acteristics of all the ceramics for a given value and size. v in v ou t i l n-fet lx i ou t c in c ou t i in esr p-fet i p-fet
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - a u g . , 2 0 1 2 a p w 7 1 5 3 / a / b w w w . a n p e c . c o m . t w 1 4 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) output capacitor selection (cont.) i lim i l i peak i out i p-fet d i l layout considerations for all switching power supplies, the layout is an impor- tant step in the design; especially at high peak currents and switching frequencies. if the layout is not carefully done, the regulator might show noise problems and duty cycle jitter. 1. the input capacitor should be placed close to the pvdd and gnd. connect the capacitor and pvdd/gnd with short and wide trace without any via holes for good input voltage filtering. the distance between pvdd/gnd to capacitor less than 2mm respectively is recommended. 2. to minimize copper trace connections that can inject noise into the system, the inductor should be placed as close as possible to the lx pin to minimize the noise coupling into other circuits. 3. the output capacitor should be place closed to vout and gnd. 4. keep the sensitive small signal nodes (fb, comp) away from switching nodes (lx) on the pcb. therefore place the feedback divider and the feedback compensa- tion network close to the ic to avoid switching noise. connect the ground of feedback divider directly to the gnd pin of the ic using a dedicated ground trace. 5. a star ground connection or ground plane minimizes ground shifts and noise is recommended. f i g u r e 1 . a p w 7 1 5 3 / a / b l a y o u t s u g g e s t i o n 5 1 8 9 10 4 3 2 7 6 rc l 1 c2 c1 cc cff r 2 r1 rt v in v out pgnd via to v out lx fb r 4 c 2 via to gnd gnd via to gnd recommended minimum footprint layout package outline 5 1 8 9 10 4 3 2 7 6 0.011 0.04 0.06 0.1 0.06 tdfn3x3-10 unit: inch 0.011 the via diameter = 0.012 hole size = 0.008 0.029 0 . 2 1 2 0 . 0 7 2 0.050 0.024 1 2 3 4 8 7 6 5 0 . 1 1 8 0.138 unit : inch sop-8p
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - a u g . , 2 0 1 2 a p w 7 1 5 3 / a / b w w w . a n p e c . c o m . t w 1 5 p a c k a g e i n f o r m a t i o n t d f n 3 x 3 - 1 0 d e pin 1 a a1 a3 b note : 1. followed from jedec mo-229 veed-5. pin 1 corner d2 e 2 l e k 0.70 0.069 0.028 0.002 0.50 bsc 0.020 bsc 0.20 0.008 k 2.90 3.10 0.114 0.122 2.90 3.10 0.114 0.122 s y m b o l min. max. 0.80 0.00 0.18 0.30 2.20 2.70 0.05 1.40 a a1 b d d2 e e2 e l millimeters a3 0.20 ref tdfn3x3-10 0.30 0.50 1.75 0.008 ref min. max. inches 0.031 0.000 0.007 0.012 0.087 0.106 0.055 0.012 0.020
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - a u g . , 2 0 1 2 a p w 7 1 5 3 / a / b w w w . a n p e c . c o m . t w 1 6 p a c k a g e i n f o r m a t i o n s o p - 8 p thermal pad d d1 e 2 e 1 e e b a 2 a a 1 view a l 0 . 2 5 gauge plane seating plane q note : 1. followed from jedec ms-012 ba. 2. dimension "d" does not include mold flash, protrusions or gate burrs. mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. dimension "e" does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 10 mil per side. 0.020 0.010 0.020 0.050 0.006 0.063 max. 0.40 l q 0 o c e e h e1 0.25 d c b 0.17 0.31 0.016 1.27 8 o c 0 o c 8 o c 0.50 1.27 bsc 0.51 0.25 0.050 bsc 0.010 0.012 0.007 millimeters min. s y m b o l a1 a2 a 0.00 1.25 sop-8p max. 0.15 1.60 min. 0.000 0.049 inches d1 2.50 0.098 2.00 0.079 e2 3.50 3.00 0.138 0.118 4.80 5.00 0.189 0.197 3.80 4.00 0.150 0.157 5.80 6.20 0.228 0.244 h x 4 5 o c see view a -t- seating plane < 4 mils
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - a u g . , 2 0 1 2 a p w 7 1 5 3 / a / b w w w . a n p e c . c o m . t w 1 7 application a h t1 c d d w e1 f 330.0 ? 2.00 50 min. 12.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 12.0 ? 0.30 1.75 ? 0.10 5.5 ? 0.05 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 tdfn3x3 - 10 4.0 ? 0.10 8.0 ? 0.10 2.0 ? 0.05 1.5+0.10 - 0.00 1.5 min. 0.6+0.00 - 0.40 3.30 ? 0.20 3.30 ? 0.20 1.30 ? 0.20 application a h t1 c d d w e1 f 330.0 ? 2.00 50 min. 12.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 12.0 ? 0.30 1.75 ? 0.10 5.5 ? 0.05 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 sop - 8p 4.0 ? 0.10 8.0 ? 0.10 2.0 ? 0.05 1.5+0.1 0 - 0.00 1.5 min. 0.6+0.00 - 0.40 6.40 ? 0.20 5.20 ? 0.20 2.10 ? 0.20 (mm) c a r r i e r t a p e & r e e l d i m e n s i o n s d e v i c e s p e r u n i t package type unit quantity tdfn3x3 - 10 tape & reel 3000 sop - 8p tape & reel 2500 a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1 h t1 a d
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - a u g . , 2 0 1 2 a p w 7 1 5 3 / a / b w w w . a n p e c . c o m . t w 1 8 t a p i n g d i r e c t i o n i n f o r m a t i o n t d f n 3 x 3 - 1 0 user direction of feed s o p - 8 p user direction of feed
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - a u g . , 2 0 1 2 a p w 7 1 5 3 / a / b w w w . a n p e c . c o m . t w 1 9 profile feature sn - pb eutectic assembly pb - free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) ( t s ) 100 c 150 c 60 - 120 seconds 150 c 200 c 60 - 1 2 0 seconds average ramp - up rate (t smax to t p ) 3 c/second ma x. 3 c/second max. liquidous temperature ( t l ) time at l iquidous (t l ) 183 c 60 - 150 seconds 217 c 60 - 150 seconds peak package body temperature (t p ) * see classification temp in table 1 see classification temp in table 2 time (t p ) ** within 5 c of the spec ified c lassification t emperature ( t c ) 2 0 ** seconds 3 0 ** seconds average r amp - down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to p eak t emperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined a s a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. c l a s s i f i c a t i o n p r o f i l e c l a s s i f i c a t i o n r e f l o w p r o f i l e s supplier t p ? t c supplier t p user t p ?? t c user t p t t s time t e m p e r a t u r e t p t l t p t c -5 o c 25 time 25 o c to peak max. ramp up rate = 3 o c/s max. ramp down rate = 6 o c/s preheat area t smax t smin t c t c -5 o c
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 6 - a u g . , 2 0 1 2 a p w 7 1 5 3 / a / b w w w . a n p e c . c o m . t w 2 0 c u s t o m e r s e r v i c e a n p e c e l e c t r o n i c s c o r p . head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 t a i p e i b r a n c h : 2 f , n o . 1 1 , l a n e 2 1 8 , s e c 2 j h o n g s i n g r d . , s i n d i a n c i t y , t a i p e i c o u n t y 2 3 1 4 6 , t a i w a n t e l : 8 8 6 - 2 - 2 9 1 0 - 3 8 3 8 f a x : 8 8 6 - 2 - 2 9 1 7 - 3 8 3 8 table 2. pb - free process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm ? 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c table 1. snpb eutectic process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 22 0 c 3 2.5 mm 220 c 220 c test item method description solderability jesd - 22, b102 5 sec, 245 c holt jesd - 22, a108 1000 hrs, bias @ t j =125 c pct jesd - 22, a102 168 hrs, 100 % rh, 2atm , 121 c tct jesd - 22, a104 500 cycles, - 65 c~150 c hbm mil - std - 883 - 3015.7 vhbm ? 2kv mm jesd - 22, a1 15 vmm ? 200v latch - up jesd 78 10ms, 1 tr ? 100ma r e l i a b i l i t y t e s t p r o g r a m c l a s s i f i c a t i o n r e f l o w p r o f i l e s ( c o n t . )

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